DSP Watch - Blowfishvhdl 0.9-beta1

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Blowfishvhdl 0.9-beta1

类型：转载作者：最后更新：2005-9-5 23:01:29 推荐指数: 1258

An implementation of the Blowfish cryptographic algorithm targetted to a Xilinx XCV1000 FPGA using Synplify and the Xilinx map/place/route tools. Everything works without a charm, and with the lowest effort level of placing and routing, the reported design speed was about 32MHz for a XCV1000-4bg560 part. It takes about 1/3 of the chip if no BlockRAMs are used. If the on chip BlockRAMs were used, it would take about 1/6th of the chip. Since the initialization arrays are static, this means you could share those arrays. If you had them share key data as well, that would reduce per-instance size as well.

Update
The design was tested with a Xilinx Virtex XCV1000-4bg560, but the VHDL code is actually written to be completely platform independant. The synthesis tools used will be what determines what hardware gets targeted. So, the design should work without a hitch on any platform that can be targeted with a VHDL synthesizer. =)

http://sourceforge.net/projects/blowfishvhdl/

资料来源：Open Collector

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