·能处理位操作、控制和DSP指令 ·电源管理包括工作模式、缓慢供电模式、以及空闲模式

at a glance:

• The OakDSPCore handles bit-manipulation, control, and DSP instructions.
• Power management includes active, slow, and idle modes.

The 16-bit, four-stage-pipeline, fixed-point, single-MAC, licensable OakDSPCore architecture includes DSP and microcontroller instructions for higher code density. It is the second member of the SmartCores family. The OakDSPCore has two data buses and one program bus, configurable ROM/RAM size, a data-address-arithmetic unit, a multiplier, a 36-bit ALU, two sets of two 36-bit accumulators, and support for a C++/C-compiler. It includes a bit-manipulation unit with a 36-bit barrel shifter, an exponent-evaluation unit that supports fast normalization, and a bit-field-operation unit. The zero-
overhead-loop mechanisms include an interruptible single-word instruction loop and four-level nesting of block repeats. User-definable registers speed hardware acceleration and provide coprocessor support. It has single-cycle interrupt latency and automatic context switching. Power management includes active-, slow-, and idle-operation modes. OakDSPCore is compatible with the PineDSPCore.

Addressing and processing modes: The OakDSPCore supports register, single and double-indirect, short- and long-immediate, short- and long index, and stack-pointer addressing modes. It supports circular (modulo) buffering for all its pointers and direct addressing for the entire 64k-word data space. It also has a program-memory-indirect addressing mode.

Special instructions or integral-peripheral functions: The OakDSPCore handles bit-manipulation, control, and DSP instructions. Instructions include single-cycle minimum/maximum calculation with pointer latching, double-precision calculations, normalization, exponent, conditional accumulator modifications, division step, read-modify (add/subtract/OR/AND/XOR)-write, test 16-bit mask bits and test bit, delayed return, interruptible single-word repeat loop and block repeat, 36-bit shift left or right in a single cycle, and a bank exchange of alternative registers.