·7个运算单元支持SIMD和MIMD指令 ·芯核提供具有16位和32位宽指令的并行性

at a glance:

• Seven arithmetic units support SIMD and MIMD instructions.
• Core offers parallelism using 16- and 32-bit-wide instruction.

PalmDSPCore is a family of three licensable, highly parallel, and dual-MAC soft DSP cores—of 16, 20, and 24 bits—targeting 2.5 and 3G terminals, voice-over-IP gateways, streaming audio/video, and infrastructure applications. PalmDSPCore is an instruction-level-parallelism architecture including MIMD (multiple-instruction-multiple-data) and SIMD (single-instruction-multiple-data) instructions and seven computation units working in parallel. The symmetrical cross-coupled MAC (multiply-accumulate) paths allow non-FIR-oriented algorithms, such as complex Radix-2 FFT butterfly, to execute in two cycles. PalmDSPCore has internal mechanisms and special instructions to reduce power consumption, in addition to active, slow, and idle power-management modes. PalmDSPCore has two multipliers; a three input ALU; a three-input split adder-subtracter unit; four orthogonal, 40/48/56-bit accumulators; and a bit-manipulation unit. The data-address arithmetic unit contains two additional adder-subtracter-units, which can perform control functions in parallel to the arithmetic calculations at the computation and bit-manipulation unit. It has zero-overhead-loop mechanisms with infinite levels of repeat and block repeat and six pipeline stages. PalmDSPCore increases code density by using variable instruction width (16 or 32 bits) so that a complete N-taps FIR filter is coded in only four words and executes in N/2+1 cycles. You can extend program memory to 32 Mbytes. PalmDSPCore is a process- and library-independent, fully synthesizable soft core, compatible with previous SmartCores generations, including Teak, TeakLite, and OakDSPCore.

Addressing and processing modes: PalmDSPCore supports circular buffering, register, short- and long-direct, short- and long-immediate, relative, bit-reversal, double-word, parallel, index-based, conditional, and stack-pointer addressing. It also supports quadruple indirect addressing mode to simultaneously feed four inputs of the two multipliers or four inputs of the split ALU.

Special instructions or integral-peripheral functions: PalmDSPCore has single, parallel, and multiparallel instruction sets that include SIMD and MIMD instructions. The core can execute as many as 18 operations in a single cycle using a 16- or 32-bit instruction width. It supports DSP and microcontroller instructions such as dual-MAC, complex FFT butterfly in two cycles, Viterbi decoding in two cycles, vector quantization, delayed branches/return, normalization, exponent, conditional instructions (parallel moves, logic, arithmetic, and accumulator), single-cycle 40/48/56-bit shift left/right, bit-field and insert-extract operations. For accelerating specific tasks, you can further extend the core with as many as 16 custom accelerators.