·DSP和控制指令集是压缩的 ·PineDSPCroe是一种可许可使用的DSP芯核

at a glance:

• The DSP-and-control instruction set is compact.
• PineDSPCore is a licensable DSP core.

PineDSPCore, the first generation of the SmartCores family, is a 16-bit, fixed-point, single-MAC (multiply-accumulate) unit, licensable DSP core. It has a compact DSP-and-control instruction set for high code density. PineDSPCore has two data buses and one program bus, a configurable ROM/RAM size, and a data-arithmetic-addressing unit. The computation unit includes a multiplier; a 32-bit product register; a 36-bit ALU; two 36-bit accumulators, including four guard bits; and a normalization mechanism. The ALU performs arithmetic and logic operations, such as step division and rounding. PineDSPCore includes two zero-overhead loop mechanisms: a single-word instruction loop and a block repeat. It has user-definable registers for hardware acceleration, coprocessor support, or both. It has three pipeline stages and single-cycle interrupt latency. Power management includes active-, slow-, and idle-operation modes.

Addressing and processing modes: PineDSPCore supports register, single- and double-indirect, and short- and long-immediate addressing modes. It has a program-memory indirect-addressing mode and supports circular (modulo) buffering for all its pointers and direct addressing for the entire 64k-word data space.

Special instructions or integral-peripheral functions: Instructions include conditional accumulator modifications, conditional and unconditional call and branch, arithmetic and logical operations, round, rotate, shift, compare, division step, MAC, square, single-word repeat loop, and block repeat.