·ST122能在600MHz下实现每秒1.2MMAC ·接口支持可定制化的协处理器

at a glance:

• The ST122 can perform 1.2 MMACs (million MACs)/sec at 600 MHz.
• Interfaces support customizable co-processors.

The general-purpose, 16-bit, fixed-point ST100 family architecture is suitable for integration into SOCs (systems on chip) targeting wired- and wireless-communications, automotive, or multimedia applications. The instruction set features DSP instructions as well as 32- and 16-bit microcontroller instructions for enhanced performance and code density. The architecture supports a 4-Gbyte memory space, 40-bit registers and accumulators, four idle modes for power-consumption reduction, and three zero-overhead nestable loops. It is scalable between high-performance and low-power operation.

Addressing and processing modes: The ST100 family supports 13 addressing modes-including circular, which suits FIR filtering, and bit reverse, which optimizes FFT implementations. Data-memory accesses handle bytes, half-words (16 bits), and words (32 bits).

Special instructions or integral-peripheral functions: The instruction set supports predication for most of its instructions, packed arithmetic, and a special instruction for Viterbi. The ST122 core supports dual 16×32-bit MAC (multiply-accumulate operations) for audio applications and multimedia-specific instructions. The ST122 subsystem includes a scalable program-cache-memory interface, which dedicated program-cache instructions control. The ST122 core can interface with as many as four tightly coupled coprocessors to improve system performance and power consumption.

Development support: STMicroelectronics and third-party partners, such as Green Hills (http://www.ghs.com/) and OSE Systems (http://www.ose.com/), offer a complete suite of evaluation boards, software-development tools, and application-software libraries to support hardware and software developments of ST100-based SOCs. Development tools are available for Windows and Unix host systems.