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·可扩展的芯核提供额外的用户定义的执行单元和指令 ·DSP选项包括双或四乘－加单元
at a glance:
Tensilica’s Xtensa V processor is a configurable, extensible, and synthesizable processor core. Designers can add DSP extensions via a Web-based configurator as well as application-specific instructions to define new registers, register files, and custom data types. The Xtensa processor generator automatically builds a correct-by-construction RTL description as well as a software tool set that incorporates the new instructions. The base architecture includes a 32-bit RISC ALU, as many as 64 general-purpose registers, and 80 base instructions, including 16- and 24-bit RISC instruction encoding with combined branch instructions, such as combined compare-and-branch and zero-overhead loops, and bit manipulations, including funnel shifts and field-extract options.
DSP engines in the Vectra family are fixed-point coprocessors for Tensilica’s Xtensa architecture. The Vectra DSP engines use an SIMD (single-instruction-multiple-date) architecture that allows vector registers to maintain data, coefficients, and intermediate results of an algorithm. The Vectra engine’s large vector register file helps reduce memory-bandwidth requirements and improves overall system performance. The Vectra engine supports single- and double-width operand sizes for greater computational accuracy. The Vectra instruction set extends the capability of the basic Xtensa microprocessor core.
Addressing and processing modes: Xtensa supports both little-endian (PC-compatible) and big-endian (Internet-compatible) address models as a configuration parameter and provides optional support for zero-overhead loops and an MMU with multiple memory-protection modes. Xtensa supports 8-, 16-, 32-, 64-, and 128-bit memory references. The Vectra DSP engine’s four addressing modes include immediate and indexed with or without updates to the base register.
Special instructions or integral-peripheral functions: Configuration options include multipliers and MACs, DSP engines, a floating-point unit, variable processor-interface width (32-, 64-, or 128-bit), big- and little-endian byte ordering, on-chip debugging, a trace port, XLMI high-speed local interface, as many as 32 interrupts, memory-management options, local data and instruction caches, and separate ROM and RAM areas. Compound instructions include special shifts, compare/branch, and zero-overhead loop instructions. Special Vectra instructions include vector operations for load/store, arithmetic (add, multiply), binary operations, and bit packing and unpacking.
Development support: Designers use the Xtensa Processor Generator to configure and extend a family of core processors with application-specific functions. The Xtensa Processor Generator also automatically generates a complete suite of development tools, including a compiler, an assembler, a linker, and a debugger that match the particular Xtensa/Vectra hardware implementation. Tensilica also provides a cycle-accurate instruction-set simulator, and a bus functional model.
Tensilica offers five main development tools, including a GNU-based software-development suite, the XCC (Xtensa C/C++ compiler), the instruction-set simulator and XTMP (Xtensa Modeling Protocol) API, the Mentor Graphics Xray debugger, and the TIE (Tensilica-instruction-extension) compiler. Third-party support includes Accelerated Technology’s (http://www.acceleratedtechnology.com/) Nucleus Plus RTOS with Xtensa OSKit for Nucleus Plus and codelab developer suite, Wind River’s (http://www.windriver.com/) VxWorks RTOS and the Tornado 2 development platform, Monta Vista’s (http://www.mvista.com/) Hard Hat Linux, Sophia Systems’ (http://www.sophia.com/) UniStac Xtensa (JTAG) in-circuit emulator, and Macraigor Systems’ (http://www.macraigor.com/) Wiggler on-chip-debugging tool. Available third-party peripheral intellectual property includes AC3 decoder, Bluetooth, G723-1 Codec, G729AB Codec, MPEG-2 AAC decoder, MPEG-4 AAC decoder, MP3 encoder, MP3 decoder, and WMA decoder.
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