·性能能从1200MIPS升级到4800MIPS ·TMS320DM642的功耗不到1.5W

at a glance:

• Performance can scale from 1200 to 4800 MIPS.
• The TMS320DM642 consumes less than 1.5W of power.

The TMS320C6000 DSP platform, a general-purpose, VLIW (very-long-instruction-word) DSP architecture, targets advanced imaging, broadband, and wireless infrastructure. This architecture includes the fixed-point C62x and C64x DSP generations and the floating-point C67x DSP generation. The C6414, C6415, and C6416 DSPs offer maximum processor speeds of 600 MHz. These processors include large on-chip memories and target video and imaging, communications, and instrumentation applications. The C6411 device targets security, communications, and office-equipment applications. It is currently the lowest priced device in the C64x lineup, and it offers the lowest power of any device in the C6000 DSP platform. The C6713 is a floating-point DSP that is an upward migration path from the C6711. It adds I²S, I²C, and S/PDIF transmit support as well as an enhanced memory space.

The TMS320DM642 is a fully programmable, 600-MHz digital media processor using a C64x core that includes integrated multimedia and communication peripherals targeting video over IP, video-on-demand, multichannel digital-video-recording applications, and video encoding and decoding. Its C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight independent functional units that include two multipliers for a 32-bit result and six ALUs with VelociTI.2 extensions. It can complete four 32-bit MAC (multiply-accumulate) operations per cycle.

The DRI200 handles the baseband processing for HD Radio and incorporates digital channel source, data decoding, and demodulation functions. The IDM combines the memory and appropriate interfaces on a credit-card-sized board. TI bases the DRI200 on the C64x core. It is compatible with iBiquity’s (http://www.ibiquity.com/) IBOC digital AM/FM system and can interface to an external microcontroller, DRAM, and SRAM. It is compatible with standard audio-DAC interfaces, includes JTAG emulation, and supports –40 to +85°C operation.

Addressing and processing modes: The C6000 DSP platform performs linear and circular addressing. Unlike other DSPs that have dedicated address-generation units, C6000 DSPs calculate addresses using one or more of its functional units. The DM642 performs dual 64-bit memory accesses each cycle and supports nonaligned memory accesses to enable sliding-window operations with SIMD (single-instruction-multiple-data) processing and circular addressing. The DM642 datapaths include support for packed data processing (SIMD), including quad 8-bit operations and dual 16-bit operations, useful for supporting video and image processing. Special instructions for key video-compression algorithms include sum-of-absolute differences for motion estimation and average instructions for motion compensation.

Special instructions or integral-peripheral functions: All C6000 DSP processors can conditionally execute all instructions, a method of reducing branching and thereby optimizing performance. On the C64x DSP, the MPYU4 instruction performs four 8×8-bit unsigned multiplies. The ADD4 instruction performs four 8-bit additions. Six of the C64x functional units can perform dual 16-bit addition/subtraction. Two of the functional units perform dual 16-bit compare, shift, minimum/maximum, and absolute-value operations. The M units also support dual 16-bit and quad 8-bit averaging operations as well as bit-expansion and bit-interleaving and -deinterleaving operations. Four of the six remaining functional units support quad 8-bit addition/subtraction operations. Two functional units support quad 8-bit compare and minimum/maximum instructions. Some instructions operate directly on packed 8- and 16-bit data. The C6411 peripheral set includes, two multichannel buffered serial ports; 32-bit, 33-MHz PCI; three timers; 64-channel enhanced DMA; and 32-bit external-memory interface. The C6414, C6415, C6416 peripheral set adds another multichannel buffered serial port, PHY interface for ATM (Utopia), and Viterbi and Turbo coprocessors.

The DM642 uses a two-level cache-based architecture. The Level 1 program cache is a 128-kbit, direct-mapped cache, and the Level 1 data cache is a 128-kbit, two-way set-associative cache. The peripheral set includes three configurable video ports; a 10/100-Mbps Ethernet media-access controller; a management data-I/O module; a VIC (VCXO interpolated control port); one multichannel buffered audio serial port; I2C bus module; two multichannel buffered serial ports; three 32-bit, general-purpose timers; a user-configurable 16- or 32-bit host-port interface; PCI; 16 general-purpose I/O pins; and a 64-bit, glueless external-memory interface that can interface to synchronous and asynchronous memories and peripherals.