·芯核能够实现单芯片多功能数字成像 ·3DSP增加的SP-20/UniPHY芯核，带有添加的IP以构成802.11a、b和g子系统

at a glance:

• Cores enable single-chip multifunction digital imaging.
• 3DSP supplemented the SP-20/UniPHY core with additional IP to build 802.11a, b, and g subsystems.

The soft-IP (intellectual-property)-core, fixed-point DSP family, bus controller, peripherals, and microprocessor interfaces from 3DSP use a scalable 32-bit SuperSIMD (single-instruction-multiple-data) architecture. The core supports multiprocessor systems, program cache or direct-mapped program memory, 32 prioritized interrupts, 32 general-purpose I/O pins, and a JTAG-only debugging interface. The SP-3 core is a programmable, five-stage-pipelined DSP that targets MP3-player, home-audio (AAC, AC3), wireless-GSM-phone, GPS, and CPE (customer-premises-equipment) VOP (voice-over-packet)-processing applications.

The SP-5 core is a programmable, superscalar, dual-issue, five-stage-pipelined DSP that targets 3G wireless, VOP gateway, xDSL, MPEG-2, MPEG-4, and wireless-LAN applications. The SP-5flex core is a fully synthesizable and configurable DSP core, based on the SP-5 architecture, which supports balancing power, cost, and performance. Designers can change the memory size, register-file size, and number of function units, and they can add application-specific instruction sets. The SP-5flex targets VOP, digital-wireless, audio, video, imaging, and broadband-modem applications. The SP-5V is a programmable, superscalar, dual-issue, five-stage-pipelined DSP that targets VOP applications.

The programmable, dual-mode, nine-stage-pipelined SP-20/UniPHY DSP IP core targets multimedia applications including multimedia over wireless. UniPhy can execute speeds of 400 MHz to 1 GHz because it supports a multiple-standard PHY implementation on the same processor. The “soft-datapath” technology and programmability enables a “softPHY” implementation that facilitates modification for changing physical-layer standards.

Special instructions or integral-peripheral functions: The 3DSP core supports two SIMD multiplier options. The first option is a dual 24×16-bit multiply that can perform two 24×16-bit multiplies, four 16×16 multiplies, or eight 8×16 multiplies in a single cycle. The second option is a dual 32×32-bit multiplier that can perform all the functions of the 24×16-bit multiplier and perform two 32×32-bit multiplies in one cycle. The 32×32-bit multiplier provides the highest quality audio processing.

The SP-20/UniPHY core combines accelerated versions of 3DSP’s SuperSIMD architecture and SP-x instruction set with an expansion-instruction mode that contains custom instructions targeting universal physical-layer signal processing for 802.11a/b/g, HiLAN2, and xDSL. Over the last year, 3DSP supplemented its SP-20/UniPHY core with additional IP to build an 802.11a, b, and g subsystem that includes a Viterbi accelerator, MAC (multiply-accumulate) accelerator, and radio interface that a suite of optimized software for the baseband and MAC (media-access controller) supports.

Development support: Offerings from 3DSP include SOC (system-on-chip) integration tools and services, including the DSP-Shuttle system-bus controller and the HiFI SOC-development environment, as well as design services, for SOC integration. Developers using the DSP-Shuttle and HiFI software can progress from concept to silicon tape-out within nine months. The company also offers optimized suites of application software for multichannel-audio and MPEG4-video streaming multimedia, VOP, and wireless-LAN support.

The DSP-Shuttle is a high-speed, fully synthesizable and configurable DSP system-bus controller, based on the proprietary Intelligent DMA technology, to address the intense data flow of DSP applications. It features real-time and high-speed data transfer, dynamic data-dependent bandwidth allocation, and multicore support. It also provides a plug-and-play uniform interface to all system peripherals and enables low-power implementation.

The GUI-based HiFI SOC integration tool enables designers to co-develop hardware and software, configure the DSP core and memory subsystem, add peripheral devices, and test performance. They can use it to perform trade-offs among clock speed, area, and power consumption. The SOC integration tool includes Software Studio—a collection of software-development tools to edit, compile, assemble, optimize, debug, and manage application code.

Sketchpad development kits allow designers to optimize and evaluate the architectures, prototype hardware, and develop application software. The kits come ready for USB plug-and-play use with a Windows-based PC. All kits include a Sketchpad FPGA development board, Software Studio, power supply, and USB cables. Designers can download candidate hardware architectures onto the development board and evaluate the performance of each configuration using software for the application.